Career Profile
Junhwan Jang received the B.S. degree in Electronics Engineering in 2025 from Sogang National University, Seoul, South Korea. He is currently the M.S. candidate in Graduate School of Semiconductor Technology in 2025 from Pohang University of Science and Technology(POSTECH), Pohang, South Korea. His current research interests include AI-based Electronic Design Automation. He is working with Prof. Seokhyeong Kang in CAD & SoC Design Lab.
Education
Experiences
Developed the parser for the powerplan, a component of PnR, using the Innovus tool.
Developed a channel data packager module for compressing and transmitting ultrasound imaging device signals
Projects
VIT hardware accelerator using HLS
- Designed an FPGA accelerator optimized for performance and time efficiency through data quantization and pipelining.